The present invention relates to a clock signal generator circuit, and more particularly to a circuit for generating a sub-clock signal having a predetermined signal width and rising in synchronization with a given main clock signal by use of the given main clock signal and an inverted delay signal to the main clock signal.
Such clock signal generator circuits are, for example, used for generating clock signals from a system clock signal and supplying the generated clock signal to a device such as a synchronous dynamic random access memory which operates in synchronizing with the system clock signal used in a memory system having a synchronous dynamic random access memory.
An example of the conventional clock signal generator circuit is shown in FIG. 8. The first conventional clock signal generator circuit has a receiver circuit 1 for receiving and waveform-shaping a system clock signal CLK1 externally inputted so as to generate a waveform-shaped internal signal S10. The first conventional clock signal generator circuit also has a delay circuit 50 connected to the receiver circuit 1 for fetching the waveform-shaped internal signal S10 and delaying and inverting the same to generate an inverted delay signal S50. The first conventional clock signal generator circuit also has a NAND gate connected to the receiver circuit 1 and the delay circuit 50 for receiving the internal signal S10 and the inverted delay signal S50 to generate a NAND logic signal. The first conventional clock signal generator circuit also has an inverter buffer connected to the NAND gate for receiving the WAND logic signal to invert the same and generate a sub-clock signal CLK2c. The system clock signal is supplied as the clock signal CLKE into the receiver circuit 1, wherein the system clock signal is supplied from the synchronous dynamic random access memory. The generated sub-clock signal CLK2c is outputted as a time-reference signal for operations of the synchronous dynamic random access memory.
NAND gate and the inverter on the next stage form an AND gate logically, for which reason in the following descriptions, the above NAND gate and the inverter deal with the AND-gate 2. There is no signal delay in signal transmission in the circuit except when the signal is intentionally delayed as the delay circuit 50 described above. No signal delay is caused in the AND gate 2 and the receiver circuit 1. The receiver circuit 1 does not play any roll in the operational principal as will be apparent from the operations described blow.
The above clock signal generator operates as follows. With reference to FIG. 9 which shows a timing chart of the circuit, in an initial state (prior to a time t10), the system clock signal CLK1 is low level. The internal signal S10 is low level. The inverted delay signal S50 is high level. The sub-clock signal CLhc is low level. At the time t10, the internal signal S10 rises from the low level to high level, whereby one input of the AND gate 2 becomes high level, whilst another input as the inverted delay signal S50 to the AND gate 2 remains high level. Therefore, the sub-clock signal CLK2c from the AND gate 2 rises from the low level to the high level at the same time when the internal signal S10 rises to high level.
After the delay time "td" by 11-stages of the delay circuit 50 has passed and the time becomes t11, the internal signal S10 reaches an output point of the delay circuit 50, whereby the inverted delay signal S50 falls from the high level down to the low level, whereby the one input of the AND gate 2 becomes low level, and thus the sub-clock signal CLK2c falls from the high level down to the low level.
Finally, at a time "t12" decided by a high level width of the system clock signal, the internal signal S10 falls from the high level down to the low level. At a time "t13" delayed by a delay time "td" from the time "t12", the inverted delay signal S50 rises from the low level to the high level, whereby the circuit returns into the initial state.
From the externally supplied system clock signal CLK1 and the inverted delay signal S50 of the system clock signal CLK1, the sub-clock signal CLK2c is generated which rises in synchronizing with the rising of the system clock signal CLK1 and has a high level width corresponding to the delay time "td".
In the industrial view point, it is preferable that the clock signal generator circuit is general and applicable to various systems rather than specific to one particular system, because stable supply and mass-production for cost reduction are possible. In the above clock signal generator circuit, however, when the high level width of the system clock signal CLK1 is narrow or the low level width thereof is narrow, the sub-clock signal may be risen with delay from the rising of the system clock signal. Even if the sub-clock signal is risen at the normal timing without delay, the sub-clock signal is fallen prior to the delay time "td". Depending upon the system clock signal, the high level width of the sub-clock signal is different from the predetermined or intended width. There was an issue to solve the above problem for responsibility to various system.
With reference again to the timing chart shown in FIG. 9, operations from the time "t10" to the time "t13" are operations of an A-system, wherein the sub-clock signal is generated which has the normal rinsing time and the normal high level width by utilizing the clock signal generator circuit. The time sequence of the transitions in level of the system clock signal CLK1 and the inverted delay signal S50 in operation of the A-system are as follows.
1 At the time "t10", the system clock signal CLK1 is risen.
2 At the time "t11", the inverted delay signal SSO is fallen.
3 At the time "t12", the system clock signal CLK1 is fallen.
4 At the time "t13", the inverted delay signal S50 is risen to return into the initial state.
Namely, the high level width of the system clock signal CLK1 is larger than the delay time "td" of the delay circuit 50. The next cycle is executed after the inverted delay signal S50 was returned into high level in the last state of the previous cycle and the delay circuit 50 has re-set into the initial state.
Operations from the time "t20" to the time "t23" in FIG. 9 are operations of a B-system, wherein the high level width of the system clock signal CLK1 is shorter than the delay time "td". In this case, the high level width of the system clock signal CLK1 is narrow. After the system clock signal or the internal signal S10 has been risen at the time "t20" and the delay time "td" has passed, and then at the time "t21", the system clock signal CLK1 returns from the high level into the low level before the inverted delay signal S50 is fallen with the delay time "td" at the time "t22". With reference to FIG. 9, when at the time "t20", the internal signal S10 is risen from the low level into the high level, then the output sub-clock signal CLK2c is risen form the low level to the high level. After the delay time "td" has passed, at the time "t22", the inverted delay signal S50 is fallen from the high level into the low level.
Before the inverted delay signal S50 is fallen at the time "t22" and the internal signal S10 inputted into the delay circuit 50 reaches the output point of the delay circuit 50, at the time "t21" internal signal S10 is fallen from the high level into the low level, whereby one input of the AND gate 2 becomes low level. Thus, at the same time when the internal signal S10 is risen, the sub-clock signal CLK2c is fallen from the high level into the low level. At the time "t23" with the delay time "td" from the falling of the internal signal S10, the inverted delay signal S50 is risen from the low level to the high level thereby returning into the initial state.
In this B-system, the high level time periods of the system clock signal CLK1 and the inverted delay signal S50 are not overlapped to each other, wherein the sub-clock signal CLK2c is risen at the time "t20" in synchronizing with rising of the system clock signal CLK1. Notwithstanding, the sub-clock signal CLK2c is fallen at the time "t21" in synchronizing with the falling of the system clock signal CLK1 at the time "t21" prior to the timing of falling inverted delay signal S50 at the predetermined falling time t22. The sub-clock signal CLK2c has the normal rising time but has the shorter high level width than the, normal width "td", wherein the high level width varies depending upon the high level width of the system clock signal CLK1.
Operations from the time "t30" to the time "t35" in FIG. 9 are operations of a C-system, wherein the low level width of the system clock signal CLK1 is shorter than the delay time "td". In this case, the low level width of the system clock signal CLK1 is narrow. After the system clock signal has been fallen at the time "t30" and the delay time "td" has passed, and then at the time "t32", the system clock signal CLK1 is risen from the low level into the high level before the inverted delay signal S50 is risen with the delay time "td" at the time "t32". With reference to FIG. 9, in this system, in the end stage of the previous cycle, states of individual signals CLK1, S10, S50, CLK2c immediately before the system clock signal CLK1 is fallen from high level to low level at the time "t30" would be the same as states of the individual signals immediately before at the time "t12" in the A-system described above. Namely, the system clock signal CLK1 is high level, the inverted delay signal S50 is low level, the sub-clock signal CLK2c is low level. In this state, at first, in the final stage of the previous cycle, at the time "t30", the system clock signal CLK1 or the internal signal S10 is fallen from the high level to the low level, whereby one input of the AND-gate 2 becomes low level. At this time, as described above, the inverted delay signal S50 as another input to the AND-gate 2 has already been in the low level, for which reason the sub-clock signal CLK2c as AND-logic output from the AND-gate 2 remains low level. In response to transfer of the above internal signal S10 from the high level to the low level, the inverted delay signal S50 is risen from the low level to the high level at the time "t32" after the delay time "td".
On the other hand, before the inverted delay signal S50 is risen at the time "t32" or at a time "t31" before the internal signal S10 inputted into the delay circuit 50 reaches an output point of the delay circuit 50, the internal signal S10 once fallen to the low level is again risen to the high level. Notwithstanding, at this time "t31", the inverted delay signal S50 as the one input to the AND-gate 2 still remains low level, for which reason the sub-clock signal CLK2c as the AND logic output from the AND-gate 2 is maintained at the low level. Thereafter, the inverted delay signal S50 is transferred to the high level. at the time "t32", whereby two inputs to the AND-gate 2 become high level. The sub-clock signal CLK2c from the AND-gate 2 is risen from the low level to the high level in synchronizing with the transfer of the inverted delay signal S50 to the high level. Thereafter, at the time "t33" later by the delay time "td" from when the internal signal S10 is risen at the time "t31", the inverted delay signal SS0 is fallen from the high level to the low level. In synchronizing with the transfer in level of the inverted delay signal S50, the output sub-clock signal CLK2c is also fallen from the high level to the low level, returning to the original state.
In this C-system, at first, the system clock signal CLK1 is fallen (at the time "t30") and then risen (at the time "t31"), and subsequently the inverted delay signal S50 is risen (at the time "t32") and then fallen (at the time "t33"). Namely, the two signals CLK1 and S50 are shifted and not overlapped. The generated sub-clock signal CLK2c is normally fallen at the time "t33" or at the fall-timing of the inverted delay signal S50, but is rapidly risen at the later time "t32" than the time "t31" of rising the system clock signal CLK1 in response to the rise of the inverted delay signal S50. As a result, the obtained output sub-clock signal CLK2c is risen with a delay from the normal timing and a high level width is shorter than a predetermined width "td" and further the high level width varies depending upon the high level width of the system lock signal CLK1.